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authorCan Celik <ogulcancelik@gmail.com>2026-09-10 21:51:57 +0300
committerGitHub <noreply@github.com>2026-09-10 21:51:57 +0300
commit425c86179791cd32e2d4ce0ae7f269940b4b0663 (patch)
treee52c4383a6d69216cbe2a32638bf90841d7e2189 /vendor/libghostty-vt/src/simd/main.zig
parent90e947a6e26e02f10ec7f1694c4eb5b78a86406b (diff)
chore: upgrade libghostty and preserve terminal behavior (#3906)
Diffstat (limited to 'vendor/libghostty-vt/src/simd/main.zig')
-rw-r--r--vendor/libghostty-vt/src/simd/main.zig12
1 files changed, 12 insertions, 0 deletions
diff --git a/vendor/libghostty-vt/src/simd/main.zig b/vendor/libghostty-vt/src/simd/main.zig
index aabdd21d..8a3f0067 100644
--- a/vendor/libghostty-vt/src/simd/main.zig
+++ b/vendor/libghostty-vt/src/simd/main.zig
@@ -9,6 +9,18 @@ pub const index_of = @import("index_of.zig");
pub const vt = @import("vt.zig");
pub const codepointWidth = codepoint_width.codepointWidth;
+/// The number of vector lanes to use for manually vectorized hot
+/// loops operating on elements of type T, or null if the target has
+/// no usable SIMD support and a plain scalar loop should be used
+/// instead (e.g. wasm32 without simd128).
+///
+/// This is twice the native vector width so that each iteration works
+/// two vector registers, giving better instruction-level parallelism.
+pub fn lanes(comptime T: type) ?comptime_int {
+ const native = std.simd.suggestVectorLength(T) orelse return null;
+ return native * 2;
+}
+
test {
@import("std").testing.refAllDecls(@This());
}